The present invention relates to a pulse width modulator that provides double pulse immunity in a high speed pulse width modulation (PWM) controller.
Pulse width modulators are often employed in motor and power controllers. Techniques for the generation of a pulse with modulated signal are well known in which a digital signal is employed to power a device or drive a motor and the duty cycle of the digital signal is varied to determine the power delivered to the load. In such a system an analog waveform is converted into a pulse width modulated signal. If the analog waveform is a generally symmetric triangular waveform, a comparator is typically used to produce both transitions of the pulse width modulated digital signal, i.e. when the portion of the analog waveform having a positive slope crosses a reference voltage, the PWM output signal transitions from a first logic state to a second logic state and when a portion of the analog waveform having a negative slope crosses the reference voltage, the PWM output signal transitions from the second logic state to the first logic state.
In a known PWM power controller a sawtooth generator is employed to provide a sawtooth waveform that is used as the analog input waveform to the comparator. The sawtooth waveform is a periodic waveform which may have a first portion in the form of a generally sloped ramp and a second portion with a rapid transitional edge. A comparator is typically employed to generate a transition in the PWM output signal from a first state to a second state when the sloped ramp crosses a reference voltage. The rapidly transitioning edge of the sawtooth typically corresponds to an edge of a clock pulse and the corresponding clock pulse edge is typically employed to generate the transition of the PWM output signal from the second state to the first state.
It is sometimes desirable to utilize a high speed comparator within the PWM controller to assure that fast rise and fall times are maintained. In a PWM controller employing an unlatched comparator, the output pulse is a function of the comparator decision. Consequently, if there is noise on the analog input signal to the comparator or on the reference input to the comparator, the comparator output may pulse on and off in response to the noise. Such undesirable pulsing can introduce an undesirable error component into the PWM output signal in the form of repeated pulses. This is known in the art as “double pulsing” in the circumstance in which a noise component introduces one or more extraneous pulses to the PWM output. In the case in which a generally symmetric triangular waveform is used as the analog input signal, noise could potentially produces double pulsing of the PWM signal at locations corresponding to reference voltage crossings by either the positive or negative going ramps of the analog input waveform.
A typical prior art PWM controller is depicted in FIG. 1. Referring to FIG. 1, a comparator 2 receives as inputs a periodic analog waveform 4 and a reference voltage 6. The comparator 2 generates a PWM output signal 8 in which the duty cycle of the signal varies with the reference voltage. The PWM output signal 8 is coupled to a driver 10 which produces a driver output signal 12. The driver output signal 12 is coupled to an output circuit 14 that provides proper biasing of the switching transistor when necessary and that includes a smooting LC filter as known in the art. The output circuit is coupled to the load 18 via the output signal 16. The PWM controller depicted in FIG. 1 is susceptible to double pulsing at the output 8 of the comparator 2 in the event of noise on the analog waveform 8 or the reference input 6.
It would therefore be desirable to have a comparator based PWM controller that can employ a high speed comparator so as to achieve fast rise and fall times while achieving double pulse immunity.